408 lines
25 KiB
HTML
408 lines
25 KiB
HTML
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<title>Assembly Intermediate Representation</title>
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<div id="contents">
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<h1><a href="index.html">Bare Bones Backend</a> / Assembly Intermediate Representation</h1>
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<p>The B3 compiler comprises two intermediate representations: a higher-level
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<a href="https://en.wikipedia.org/wiki/Static_single_assignment_form">SSA</a>-based
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representation called <a href="intermediate-representation.html">B3 IR</a> and a lower-level
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representation that focuses of machine details, like registers. This lower-level form is called
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Air (Assembly Intermediate Representation).</p>
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<p>Air programs are represented using a
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<a href="http://trac.webkit.org/browser/trunk/Source/JavaScriptCore/b3/air/AirCode.h"><code>Air::Code</code></a>
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object. <code>Code</code> comprises an array of
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<a href="http://trac.webkit.org/browser/trunk/Source/JavaScriptCore/b3/air/AirBasicBlock.h">basic
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blocks</a>. Each basic block comprises an array of
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<a href="http://trac.webkit.org/browser/trunk/Source/JavaScriptCore/b3/air/AirInst.h"><code>Inst</code></a>s.
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Air has an explicit control flow graph: each basic block has predecessor and successor blocks.
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Execution always begins at the first basic block (<code>code[0]</code>). The <code>Inst</code>s
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in each block are executed in order. Each <code>Inst</code> has an opcode, some flags, an
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array of arguments
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(<a href="http://trac.webkit.org/browser/trunk/Source/JavaScriptCore/b3/air/AirArg.h"><code>Arg</code></a>s),
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and an origin. The opcode and flags are wrapped in a <code>Kind</code>, to make it
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convenient to carry them around together. The origin is simply a B3 IR
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<a href="http://trac.webkit.org/browser/trunk/Source/JavaScriptCore/b3/B3Value.h"><code>Value</code></a>.
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Some opcodes use the origin for additional meta-data. This works because Air code always
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coexists with the B3 procedure from which it was generated.</p>
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<p>This document begins by describing the philosophy of Air. The behavior of <code>Arg</code>s is
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central to Air's execution model, which is described in the section that follows. The last
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section describes the way Air opcodes are defined.</p>
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<h2>Philosophy of Air</h2>
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<p>B3 is designed to be portable to many kinds of CPUs. Currently, it supports x86-64 and ARM64,
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which are quite different from each other. In B3 IR, we expose very few instruction set
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details. It's a goal of B3 IR to ensure that B3 values behave the same way except when the
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alternative would be counterproductive (like with pointer size, the corner-case behaviors of
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division, or calling convention customization). But to effectively compile code to different
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CPUs, the compiler has to eventually make instruction set details explicit. This is where Air
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comes in. B3 locks in most CPU-specific details at the moment of conversion to Air, and the Air
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code is irreversibly tied to some specific CPU.</p>
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<p>Air is an instruction <i>superset</i>: it recognizes all of the instructions from all CPUs
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that Air may target. In its lowest-level form, Air is simply a way of describing an assembly
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instruction sequence, and this includes CPU concepts like registers and direct accesses to the
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stack. Air also has a higher-level form in which the assembly has not yet undergone register
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or stack allocation. Therefore, Air also supports abstract registers (called
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<a href="http://trac.webkit.org/browser/trunk/Source/JavaScriptCore/b3/air/AirTmp.h"><code>Tmp</code></a>s)
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and abstract
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<a href="http://trac.webkit.org/browser/trunk/Source/JavaScriptCore/b3/air/AirStackSlot.h">stack
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slots</a>. A <code>Tmp</code> object can either hold an unallocated temporary or a
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register.</p>
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<h3>Air as an Instruction Superset</h3>
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<p>Air has syntax to speak of all of the CPU instructions we know about. It is possible to speak
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of an x86-64 instruction while compiling for ARM64, for example. Clients of Air, such as the B3
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to Air lowering phase, are allowed to pick any Air opcode and ask if that opcode would be
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valid on the current CPU. They are also allowed to check if specific forms of any given opcode
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are valid. This allows clients to optimize for multiple instruction sets by cascading through
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the possible opcodes that they know of, starting with the one they think is most efficient.
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Some of those opcodes may only be available on one CPU while others are available
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everywhere. Instruction selection does not need to know which instructions work on which CPUs;
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Air will tell you if some instruction happens to not be valid right now for whatever reason.</p>
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<p>Air opcodes support overloading. For example, the Add32 opcode has both two-operand and
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three-operand <i>overloads</i>, and those overloads have multiple <i>forms</i>: the first
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operand may or may not be permitted to be an immediate and depending on the CPU and some of the
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other operands may or may not be allowed to be memory addresses. We use <i>opcode overload</i>
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to refer to all forms of an opcode that share the same number of arguments, and <i>opcode
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form</i> to mean the number of arguments and their types. A fundamental Air operation is
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<code>Inst::isValidForm()</code>, which tells the client if the instruction's current form is
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valid on the current CPU. This may return false either because the Inst is not well-formed for
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any CPU or because it is not valid for the current CPU even though it may be valid on some
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other CPU. There is also <code>Air::isValidForm()</code>, which can answer if the form you are
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intending to use will be valid even if you have not created an <code>Inst</code> yet. This
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allows clients to generate Air by experimenting with different forms before settling on the one
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that the current CPU supports.</p>
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<h3>Air as a High-Level Assembly</h3>
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<p>Air doesn't require the client to perform register or stack allocation. Anywhere that Air
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accepts a register it will also accept a <code>Tmp</code>. Anywhere that Air accepts an address
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it will also accept a stack slot reference. Air code generation comprises a register allocator
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and a stack allocator, which turn <code>Tmp</code>s into <code>Reg</code>s and stack slots into
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addresses with the frame pointer (or stack pointer) as the base and some integer offset. Air
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allows clients to speak of registers directly even while also using <code>Tmp</code>s, and the
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register allocator will ensure that it avoids clobbering registers that the client code already
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relies upon. This is possible because Air has precise modeling of how instructions use
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registers, so it's always possible to determine which registers are live at any point in the
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Air code.</p>
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<p>Air's philosophy allows B3 to use it for converting high-level, mostly-CPU-agnostic SSA
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procedures into code for the current CPU. Air is an instruction superset that allows clients to
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consider all available instructions on all possible CPUs and query which forms of those
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instructions are available on the current CPU. Air also supports for high-level concepts like
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<code>Tmp</code>s and stack slots, which allows B3 to Air lowering to focus on which
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instructions to use without worrying about register allocation or stack layout.</p>
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<h2>Args and the Air Execution Model</h2>
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<p>Air can be thought of as an
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<a href="https://en.wikipedia.org/wiki/Orthogonal_instruction_set">orthogonal instruction
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set</a>. It's possible to construct an <code>Inst</code> with any combination of opcode and
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arguments. The opcode determines what Air will do to the arguments - it may read from them or
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write to them, for example. Orthognality implies that any argument that is read may be either
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a register (or <code>Tmp</code>), an address, or an immediate; while any argument that is
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written may be either a register or an address. Air constrains orthognality where the target
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CPU would. For example, none of Air's target CPUs would support an <code>Add32</code>
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instruction that loads its sources from memory <i>and</i> stores its result into memory. Even
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x86 doesn't go that far. Either before or after creating an <code>Inst</code>, the client can
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query if a particular combination of arguments (for example, three memory addresses) would be
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valid for a given opcode (for example, <code>Add32</code>).</p>
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<p>Air arguments are represented using the <code>Arg</code> object. <code>Arg</code> can
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represent any of the following assembly operands:</p>
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<dl>
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<dt>Tmp</dt>
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<dd>A <code>Tmp</code> represents either a register or a temporary.</dd>
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<dt>Imm, BigImm, BitImm, and BitImm64</dt>
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<dd>These are various kinds of immediates. We distinguish between big and small immediates
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because some instructions only allow immediates within a certain range. We distinguish
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between immediates for bit operations and immediates for all other operations because ARM
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has different constraints on the values of immediates depending on whether they are used for
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bit math.</dd>
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<dt>Addr, Stack, CallArg, and Index</dt>
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<dd>These are all memory addresses. Addr is a base-offset address, which uses a <code>Tmp</code>
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for the base and an immediate for the offset. Stack and CallArg are abstract stack offsets.
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Index is a base-index address, which has a pair of <code>Tmp</code>s (base and index) as well
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as an offset immediate and a scaling immediate for the index.</dd>
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<dt>RelCond, ResCond, and DoubleCond</dt>
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<dd>These are condition codes for various kinds of branches.</dd>
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<dt>Special</dt>
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<dd>Air allows certain <code>Inst</code>s to point to additional meta-data. The Special
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argument type is used for such meta-data. It holds a <code>Arg::Special*</code>.</dd>
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<dt>WidthArg</dt>
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<dd>Some special Air opcodes take operands that describe the width of the operation. Possible
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values are <code>Width8</code>, <code>Width16</code>, <code>Width32</code>, and
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<code>Width64</code>.</dd>
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</dl>
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<p>The opcode of an <code>Inst</code> combined with the overload - i.e. the number of arguments
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- determines what the <code>Inst</code> will do to each argument. The behavior of arguments
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comes down to three dimensions that are determined by the opcode and overload:</p>
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<dl>
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<dt>Role</dt>
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<dd>The role of an argument is an enum that describes the timing of when the argument is
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accessed, how it's accessed (use, a.k.a. read; or def, a.k.a write), how important that
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access is for performance (either <i>warm</i> or <i>cold</i>), and how writes affect the top
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bits (either ignores them or zero-fills them). The timing of an argument role is discussed
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further below. The performance requirements of an argument are used for register allocation
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prioritization. A warm argument is counted towards the register allocation priority
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heuristic, while a cold one isn't.</dd>
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<dt>Type</dt>
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<dd>Air recognizes two types, <code>GP</code> (general purpose) and <code>FP</code> (floating
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point). Arguments also have type. It's important to remember that there is both a type for
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the argument as determined by the opcode and overload, and a type of the argument itself.
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Some arguments are untyped, which means that they may be used regardless of the type desired
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by the opcode/overload. For example, addresses are untyped. Other arguments have specific
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type, like registers and <code>Tmp</code>s. Except for <code>BigImm</code>, immediates are
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<code>GP</code>.</dd>
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<dt>Width</dt>
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<dd>The amount of bits, starting at lowest-order, that the instruction affects. Possible values
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are <code>Width8</code>, <code>Width16</code>, <code>Width32</code>, and
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<code>Width64</code>.</dd>
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</dl>
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<p>The timing of an argument role is important, and brings us to the order of execution of an
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<code>Inst</code>. Each <code>Inst</code> can be thought of as executing three
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steps:</p>
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<ol>
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<li>Perform <i>early</i> actions.</li>
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<li>Perform <i>primary</i> actions.</li>
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<li>Perform <i>late</i> actions.</li>
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</ol>
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<p>The early actions of one instruction happen immediately after the late actions of
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the instruction before it. However, many Air analyses view them as happening at the same time.
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For example, any register usage in the early action of one instruction interferes with the
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register usage in the late action of the instruction that came before it. All of Air's
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liveness and interference analyses reason about the
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<a href="https://en.wikipedia.org/wiki/Off-by-one_error#Fencepost_error"><i>fence posts</i></a>
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between instructions, where the late actions of the previous instruction and the early actions
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of the next form an interference clique.</p>
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<p>Let's consider a simple example, like <code>Add32</code> with two arguments. Let's say that
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the first argument is a memory location and the second argument is a register. Air uses the
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<a href="https://en.wikipedia.org/wiki/X86_assembly_language#Syntax">AT&T style</a> of
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placing the destination argument last for most instructions. This Add32 loads from memory and
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adds the value to the register. Air writes this as:</p>
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<pre><code>Add32 42(%rax), %rcx</code></pre>
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<p>This instruction will proceed in three steps:</p>
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<ol>
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<li>Load the value at offset 42 from the memory address in <code>%rax</code>. The result is
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stored in an internal, hidden CPU location for the remainder of execution. Even if the
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instruction later stores to memory and overwrites this value, <code>Add32</code> will still
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use the original value it had loaded. We say that this is an <i>early use</i>. At the same
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time, the CPU will load the value of <code>%rcx</code> and store it in a hidden CPU
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location. This is also an early use.</li>
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<li>Add the two values together. Store the result in hidden CPU location.</li>
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<li>Zero-extend the resulting value and store it into <code>%rcx</code>. This is a <i>late
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def with zero extension</i>.</li>
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</ol>
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<p>Therefore, the two-argument overload of <code>Add32</code> ascribes the following to its
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arguments:</p>
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<ul>
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<li>The roles are <i>early warm use</i> for the first argument (<code>42(%rax)</code>) and
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<i>early warm use with late warm def with zero extension</i> for the second argument
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(<code>%rcx</code>). Early warm use is written as <code>Use</code> for short. Early warm
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use with late warm def with zero extension is written as <code>UseZDef</code> for
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short.</li>
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<li>The types of both arguments are <code>GP</code>. This matches <code>42(%rax)</code> because
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addresses match any type. This matches <code>%rcx</code> because it's a general-purpose
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register.</li>
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<li>The widths of both arguments are <code>Width32</code>. Combined with <code>UseZDef</code>,
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this means that the instruction will read the low 32 bits of <code>%rcx</code> in the early
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actions and it will store to <i>all</i> bits of <code>%rcx</code> in the late actions, but it
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will ensure that all but the low 32 bits are zero.</li>
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</ul>
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<p>Air can tell you what role, type, and width is ascribed to each argument by using the
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<code>Inst::forEachArg(func)</code> operation. It takes a callback of type
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<code>void(Arg&, Arg::Role, Arg::Type, Arg::Width)</code>. For our <code>Add32</code> example,
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this callback would get called twice:</p>
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<ol>
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<li><code>func(42(%rax), Use, GP, Width32)</code></li>
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<li><code>func(%rcx, UseZDef, GP, Width32)</code></li>
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</ol>
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<p>It's important to remember that Air's summaries of what instructions do to arguments are
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not meant to be exhaustive. For example, if an instruction claims to use an address, this
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tells you that the instruction will perform a load but it tells you nothing about how that
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load will be performed. This means that unless you know exactly what it means to use/def an
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argument, you cannot perform this transformation:</p>
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<ul>
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<li>Before:
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<pre><code>Foo32 (%rax)</code></pre></li>
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<li>After:
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<pre><code>Move32 (%rax), %tmp
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Foo32 %tmp</code></pre></li>
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</ul>
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<p>Even if you know that Foo32 only uses its argument, you cannot do this because Move32 may
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not load from the address using exactly the same kind of load that Foo32 would have done.
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Memory accesses have many dimensions of options: alignment semantics (if you're lucky then
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misaligned accesses run fast but sometimes they ignore low bits, trap if unaligned, or run
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super slow when unaligned, and this behavior may depend on the opcode), temporality and
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memory ordering, determinism of trapping, etc. Just seeing that an instruction uses an
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address does not tell you what kind of load will happen, and currently Air does not have the
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ability to answer such questions. Fortunately, Air does not have much need to move memory
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accesses out of instructions. Uses and defs of temporaries, registers, immediates, and spill
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slots don't have these caveats and so those arguments can be moved from one instruction to
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another without worries.</p>
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<p>Air's introspection of <code>Inst</code>s tends to be quite fast thanks to the use of template
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specialization and C++ lambdas. The <code>forEachArg()</code> template method uses an efficient
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arrangement of switch statements to determine the opcode and overload. If <code>func</code> is
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a C++ lambda, we expect <code>forEachArg()</code> to be specialized for that lambda. Therefore,
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this idiom avoids virtual dispatch or memory allocation.</p>
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<p>Air supports exotic roles, such as late uses and early defs. There is even the
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<code>Scratch</code> role, which means early def and late use. Speaking of a <code>Tmp</code>
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in the <code>Scratch</code> role means that the <code>Tmp</code> will be assigned a register
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that is guaranteed to not interfere with any of the other registers that the instruction
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speaks of. Late uses and early defs are crucial for patchpoints, which may require
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that one of the incoming values be given a register that does not interfere with whatever
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register is used for the result. This can be expressed either as giving the inputs a late use
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role or by giving the outputs an early def role. The full list of possible roles is:</p>
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<dl>
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<dt>Use</dt>
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<dd>Early warm use.</dd>
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<dt>ColdUse</dt>
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<dd>Early cold use.</dd>
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<dt>LateUse</dt>
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<dd>Late warm use.</dd>
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<dt>LateColdUse</dt>
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<dd>Late cold use.</dd>
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<dt>Def</dt>
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<dd>Late def. <i>Note that all defs are warm.</i></dd>
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<dt>ZDef</dt>
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<dd>Late def with zero-extension.</dd>
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<dt>UseDef</dt>
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<dd>Early warm use and late def.</dd>
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<dt>UseZDef</dt>
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<dd>Early warm use and late def with zero extension.</dd>
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<dt>EarlyDef</dt>
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<dd>Early def.</dd>
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<dt>Scratch</dt>
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<dd>Early def and late warm use.</dd>
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<dt>UseAddr</dt>
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<dd>Early warm use of the address's components.</dd>
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</dl>
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<p><code>UseAddr</code> is interesting for the <code>Lea</code> (load effective address)
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instruction, which evaluates the address and places the result into a temporary or register.
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The argument must be an address, but <code>UseAddr</code> means that we don't actually read
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from the address. Note that using an address in any of the other roles always implies that the
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components of the address are used early and warm (i.e. <code>Use</code>).</p>
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<p>Air arguments are central to Air's execution model. The early and late actions of an
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instruction have to do with arguments, and what happens to each argument during the early and
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late actions is determined by the opcode and the number of arguments (i.e. the overload).
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Clients of Air may create an <code>Inst</code> with any combination of opcode and arguments
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and then query, using <code>isValidForm()</code> if the opcode, overload, and specific
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arguments are valid for the current CPU.</p>
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<h2>Defining Air</h2>
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<p>Air has many opcodes and the opcodes have many different overloads and forms. Air makes it
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easy to reason about all of them with helpers like <code>isValidForm()</code> and
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<code>forEachArg()</code>. It also provides a <code>Inst::generate()</code> function that will
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generate code for the instruction, provided that it does not use any non-register
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<code>Tmp</code>s or any abstract stack slots. If we wrote the
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code for validating, iterating, and generating each form by hand, we would have a bad time.
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For this reason, Air comes with an
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<a href="http://trac.webkit.org/browser/trunk/Source/JavaScriptCore/b3/air/opcode_generator.rb">opcode code generator</a>
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that uses a
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<a href="http://trac.webkit.org/browser/trunk/Source/JavaScriptCore/b3/air/AirOpcode.opcodes">opcode definition file</a>
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as input. The opcode definition file use a simple and concise syntax that lets us define many
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opcodes at once and constrain them to the CPU kinds that support them. Additionally, Air
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supports <i>custom</i> opcodes, where the code generator emits calls to
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<a href="http://trac.webkit.org/browser/trunk/Source/JavaScriptCore/b3/air/AirCustom.h">hand-written
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C++ code</a>. This section describes the opcode definition language.</p>
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<p>It's easiest to understand the opcode definitions with an example. Let's use the two-argument
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overload of <code>Add32</code>.</p>
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<pre><code>Add32 U:G:32, UZD:G:32
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Tmp, Tmp
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x86: Imm, Addr
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x86: Imm, Index
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Imm, Tmp
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x86: Addr, Tmp
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x86: Tmp, Addr
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x86: Tmp, Index</code></pre>
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<p>The first line defines the overload. It has two arguments. The first argument serves the
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<code>Use</code> role, shorted as <code>U</code>. It is general-purpose, shortened as
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<code>G</code>. It has a 32-bit width. Hence the string <code>U:G:32</code>. Similarly,
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<code>UZD:G:32</code> means <code>UseZDef</code>, <code>GP</code>, <code>Width32</code>.</p>
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<p>The next lines list the available forms of the overload. A form is a list of possible kinds of
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arguments. These use the same terminology for <code>Arg</code> kinds from the previous section,
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with the caveat that <code>Addr</code> implies that <code>Addr</code>, <code>Stack</code>, or
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<code>CallArg</code> would be accepted.</p>
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<p>Prefixing any line with <code>x86:</code> means that this form is only available on x86
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CPUs, such as x86 or x86-64.</p>
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<p>Air opcodes are designed to work with JavaScriptCore's existing MacroAssembler. By default, an
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|
opcode is automatically given a code generator that calls
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<code>MacroAssembler::<i>opcodeName</i></code>, where <i>opcodeName</i> is derived by
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|
lower-casing the first letter of the Air opcode name. <code>Add32</code> becomes
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<code>MacroAssembler::add32</code>, for example.</p>
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<p>See the header of
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<a href="http://trac.webkit.org/browser/trunk/Source/JavaScriptCore/b3/air/AirOpcode.opcodes">AirOpcode.opcodes</a>
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for a complete list of shorthand used by Air's opcode definition language.</p>
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<h2>Summary</h2>
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<p>Air is designed around JavaScriptCore's existing MacroAssembler. Air has Inst objects,
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which each describe some method call to the MacroAssembler: an Inst's opcode indicates
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which method name to use and its args indicate the arguments to pass to that method. We
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|
use code generation to create a massive switch statement that turns the reflective Insts
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|
into actual calls to MacroAssembler. Consequently, we can "add" new instructions to Air
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usually by just editing the <a href="http://trac.webkit.org/browser/trunk/Source/JavaScriptCore/b3/air/AirOpcode.opcodes">AirOpcode.opcodes</a>
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file.</p>
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</body>
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</html>
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