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haikuports/sci-electronics/verilator/verilator-3.864.recipe

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SUMMARY="A fast C++ Verilog simulator"
DESCRIPTION="Verilator is the fastest free Verilog HDL simulator, and \
beats most commercial simulators. It compiles synthesizable Verilog (not \
test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions \
into C++ or SystemC code. It is designed for large projects where fast \
simulation performance is of primary concern, and is especially well suited \
to generate executable models of CPUs for embedded software design teams."
HOMEPAGE="https://www.veripool.org/wiki/verilator"
COPYRIGHT="2006-2014 Wilson Snyder"
LICENSE="GNU GPL v3"
REVISION="3"
SOURCE_URI="http://www.veripool.org/ftp/verilator-3.864.tgz"
CHECKSUM_SHA256="f6734c2aa33946357d5abfd9211b4206297f9adf07dfc3186cbbba0d8c8842af"
PATCHES="verilator-$portVersion.patchset"
ARCHITECTURES="all"
SECONDARY_ARCHITECTURES="x86"
PROVIDES="
verilator$secondaryArchSuffix = $portVersion
cmd:verilator$secondaryArchSuffix
cmd:verilator_bin$secondaryArchSuffix
cmd:verilator_bin_dbg$secondaryArchSuffix
cmd:verilator_profcfunc$secondaryArchSuffix
"
REQUIRES="
haiku$secondaryArchSuffix
"
BUILD_REQUIRES="
haiku${secondaryArchSuffix}_devel
"
BUILD_PREREQUIRES="
cmd:awk
cmd:bison
cmd:flex
cmd:gcc$secondaryArchSuffix
cmd:make
cmd:perl
"
BUILD()
{
runConfigure ./configure
make $jobArgs
}
INSTALL()
{
make install
}
TEST()
{
make check
}